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24LC01B/02B
1K/2K 2.5V I2CTM Serial EEPROM
FEATURES
* Single supply with operation down to 2.5V * Low power CMOS technology - 1 mA active current typical - 10 A standby current typical at 5.5V - 5 A standby current typical at 3.0V * Organized as a single block of 128 bytes (128 x 8) -1K or 256 bytes (256 x 8) -2K * 2-wire serial interface bus, I2CTM compatible * 100 kHz (2.5V) and 400kHz (5.0V) compatibility * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 8 bytes * 2 ms typical write cycle time for page-write * Hardware write protect for entire memory * Can be operated as a serial ROM * ESD protection > 3,000V * 1,000,000 E/W cycles guaranteed * Data retention > 200 years * 8 pin DIP, SOIC, TSSOP* or SOT-23* package * Available for temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C
PACKAGE TYPES
PDIP, SOIC A0 A1 A2 Vss 1 24LC01B/02B 2 3 4 8 7 6 5 Vcc WP SCL SDA
TSSOP* 24LC01B/02B
A0 A1 A2 VSS
1 2 3 4
8 7 6 5
Vcc WP SCL SDA
SOT-23* SCL VSS SDA 1 2 3 5 WP 24LC01B
DESCRIPTION
The Microchip Technology Inc. 24LC01B and 24LC02B are 1K bit and 2K bit Electrically Erasable PROMs. The devices are organized as a single block of 128 x 8 bit or 256 x 8 bit memory with a two wire serial interface. Low voltage design permits operation down to 2.5 volts with a standby and active currents of only 5 A and 1 mA respectively. The 24LC01B and 24LC02B also have page-write capability for up to 8 bytes of data. The 24LC01B and 24LC02B are available in the standard 8-pin DIP and an 8-pin surface mount SOIC package. The SOT-23 and TSSOP packages are available for the 24LC01B.
4
Vcc
* Available for 24LC01B only
BLOCK DIAGRAM
WP
HV GENERATOR
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
SDA SCL
YDEC
VCC VSS
SENSE AMP R/W CONTROL
* Available for 24LC01B only
(c) 1999 Microchip Technology Inc.
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DS20071J-page 1
24LC01B/02B
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name VSS SDA SCL WP VCC A0, A1, A2
PIN FUNCTION TABLE
Function Ground Serial Address/Data I/O Serial Clock Write Protect Input +2.5V to 5.5V Power Supply No Internal Connection
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins.............................................> 3 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
VCC = +2.5V to +5.5V Parameter Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS -10 -10 -- -- -- -- .05 VCC Min. .7 VCC .3 VCC -- .40 10 10 10 3 1 30 100 Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Max. Units V V V V A A pF mA mA A A VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC WP = VSS (Note) IOL = 3.0 mA, VCC = 2.5V VIN = .1V to 5.5V VOUT = .1V to 5.5V VCC = 5.0V (Note 1) Tamb = 25C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz Conditions
WP, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmidt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL TSU:STA SDA THD:STA TSU:STO
START
STOP
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24LC01B/02B
TABLE 1-2: AC CHARACTERISTICS
Standard Mode Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Symbol Min. FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max. 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc = 4.5 - 5.5V Fast Mode Min. -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max. 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Units
Remarks
Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance
TOF TSP TWR --
-- -- -- 1M
250 50 10 --
20 +0.1 CB -- -- 1M
250 50 10 --
ns ns ms
cycles 25C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA SDA IN THD:STA TSP TAA SDA OUT THD:STA THD:DAT TSU:DAT TSU:STO
TAA
TBUF
(c) 1999 Microchip Technology Inc.
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DS20071J-page 3
24LC01B/02B
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24LC01B/02B supports a bi-directional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC01B/02B works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24LC01B/02B does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
FIGURE 3-1:
(A) SCL (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
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24LC01B/02B
3.6 Devise Address
4.0
4.1
WRITE OPERATION
Byte Write
The 24LC01B/02B are software-compatible with older devices such as 24C01A, 24C02A, 24LC01, and 24LC02. A single 24LC02B can be used in place of two 24LC01's, for example, without any modifications to software. The "chip select" portion of the control byte becomes a don't care. After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24LC01B/02B, followed by three don't care bits. The eighth bit of slave address determines if the master device wants to read or write to the 24LC01B/02B (Figure 3-2). The 24LC01B/02B monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. Operation Read Write Control Code 1010 1010 Chip Select XXX XXX R/W 1 0
Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC01B/02B. After receiving another acknowledge signal from the 24LC01B/02B the master device will transmit the data word to be written into the addressed memory location. The 24LC01B/02B acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC01B/02B will not generate acknowledge signals (Figure 4-1).
4.2
Page Write
FIGURE 3-2:
START
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
X = Don't care
The write control byte, word address and the first data byte are transmitted to the 24LC01B/02B in the same way as in a byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the 24LC01B/02B which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2).
Note:
Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
(c) 1999 Microchip Technology Inc.
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DS20071J-page 5
24LC01B/02B
FIGURE 4-1:
BUS ACTIVITY MASTER
BYTE WRITE
S T A R T CONTROL BYTE WORD ADDRESS DATA S T O P
SDA LINE
S
A C K A C K A C K
P
BUS ACTIVITY
FIGURE 4-2:
BUS ACTIVITY MASTER
PAGE WRITE
S T A R T CONTROL BYTE WORD ADDRESS (n) S T O P
DATA n
DATAn + 1
DATAn + 7
SDA LINE
S
A C K A C K A C K A C K A C K
P
BUS ACTIVITY
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24LC01B/02B
5.0 ACKNOWLEDGE POLLING 7.0 READ OPERATION
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
7.1
Current Address Read
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The 24LC01B/02B contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC01B/02B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC01B/02B discontinues transmission (Figure 7-1).
7.2
Send Stop Condition to Initiate Write Cycle
Random Read
Send Start
Send Control Byte with R/W = 0
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC01B/02B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC01B/ 02B will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC01B/02B discontinues transmission (Figure 7-2). NO
Did Device Acknowledge (ACK = 0)? YES Next Operation
7.3
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24LC01B/02B transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC01B/02B to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24LC01B/02B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.
6.0
WRITE PROTECTION
The 24LC01B/02B can be used as a serial ROM when the WP pin is connected to VCC. Programming will be inhibited and the entire memory will be write-protected.
7.4
Noise Protection
The 24LC01B/02B employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
(c) 1999 Microchip Technology Inc.
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DS20071J-page 7
24LC01B/02B
FIGURE 7-1: CURRENT ADDRESS READ
S T A R T CONTROL BYTE S T O P
BUS ACTIVITY MASTER
DATA n
SDA LINE
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 7-2:
RANDOM READ
CONTROL BYTE WORD ADDRESS (n) S T A R T CONTROL BYTE S T O P
S T BUS ACTIVITY A MASTER R T SDA LINE
DATA n
S
A C K A C K
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 7-3:
SEQUENTIAL READ
DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P
BUS ACTIVITY CONTROL BYTE MASTER
SDA LINE
P
A C K A C K A C K A C K N O A C K
BUS ACTIVITY
8.0
8.1
PIN DESCRIPTIONS
SDA Serial Address/Data Input/Output
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10K3/4 for 100 kHz, 2 K3/4 for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
8.3
WP
This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected.
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24LC01B/02B
NOTES:
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DS20071J-page 9
24LC01B/02B
NOTES:
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24LC01B/02B
24LC01B/02B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24LC01B/02B -- /P P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead Package: SM = Plastic SOIC (207 mil Body), 8-lead OT = SOT-23, 5-lead (24LC01B only) ST = TSSOP, 8-lead (24LC01B only) Temperature Range: Blank = 0C to +70C I = -40C to +85C 24LC01B Device: 24LC01BT 24LC02B 24LC02BT 1K I2C Serial EEPROM 1K I2C Serial EEPROM (Tape and Reel) 2K I2C Serial EEPROM 2K I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
AMERICAS (continued)
Toronto
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ASIA/PACIFIC (continued)
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ASIA/PACIFIC
Hong Kong
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EUROPE
United Kingdom
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Germany
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11/15/99
Shanghai
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New York
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San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
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